Market demand for microprocessor performance has  motivated  continued scaling of CMOS through a succession of lithography  generations. Quantum mechanical limitations to continued scaling are  becoming readily apparent. Partially Depleted Silicon-on-Insulator  (PD-SOI) technology is emerging as a promising means of addressing  these limitations. It also introduces additional design complexity  which must be well understood.   SOI Circuit Design Concepts first introduces the student or  practising engineer to SOI device physics and its fundamental  idiosyncrasies. It then walks the reader through realizations of these  mechanisms which are observed in common high-speed microprocessor  designs. Rules of thumb and comparisons to conventional bulk CMOS are  offered to guide implementation. SOI's ultimate advantage, however,  may lie in the unique circuit topologies it supports; a number of  these novel new approaches is also described.   SOI Circuit Design Concepts draws upon the latest industry  literature as well as the firsthand experiences of its authors. It is  an ideal introduction to the concepts of governing SOI use and  provides a firm foundation for further study of this exciting new  technology paradigm.

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